Design Studio

Design visually, then get real Verilog and a testbench that checks it. Everything runs in your browser; open the result in the Sandbox to simulate it.

⏚

Circuit editor

Wire gates, flip-flops, switches and LEDs on a canvas and watch the circuit run live, then export Verilog with a testbench.

◎

FSM designer

Draw a Moore or Mealy state machine, step it clock by clock, and get Verilog with a testbench that checks every cycle.

⎍

Timing diagram

Draw waveforms cycle by cycle (or sample them from a simulation), export SVG, PNG or WaveJSON, and test a design against them.

⊞

Truth table & K-map

Fill in a truth table to get the K-map groups, the minimal sum-of-products and product-of-sums, and Verilog with a testbench that checks every row.